ARM/FPGA graphics, sound and IPC on DE1-SoC Cyclone5 Dev board

Project Status
In Progress
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Difficulty
Difficulty

Check out this list of some of the items you'll need to complete this project.

Skills Overview

Here are some of the skills you'll need to complete this project:

The Challenge

The Intel/Altera Cyclone5 FPGA on DE1-SOC board has programmable logic, dual ARM9 CPUs, and a variety of peripherials, including VGA interface and audio codec. Getting it to work together is complicated and interesting. Starting one process to write to the video buffer as fast as possible, and keep the audio FIFO filled, failed above about 8000 pixels per loop, where the FIFO could be filled in each loop if there was space. The easy solution is to start two processes, which are migrated by Linux onto the two processors with both running at full speed. Starting two processes to maximize bandwidth, requires communication between the processes. This example uses the fixed audio synthesis frequency (48 KHz) to drive a timer/counter which then uses shared memory IPC (interprocess communication) to display the time on the VGA.

Details

--Using two ARM processors to write video and play a tone.
Starting one process to write to the video buffer as fast as possible, and keep the audio FIFO filled, failed above about 8000 pixels per loop, where the FIFO could be filled in each loop if there was space. The easy solution is to start two processes, which are migrated by Linux onto the two processors with both running at full speed. (Quartus archivecombined audio/videocode which failed at high write-rates). The audio code required the math library for sine wave synthesis, which requires compile with the -lm option. The video code is unchanged. The address header describes the memory-mapped view of the FPGA seen by the ARMs. The details of FPGA hardware are available in the link at the end.

--Using two ARM processors with IPC to display time while writing video and playing a tone.

Starting two processes to maximize bandwidth, requires communication between the processes. This example uses the fixed audio synthesis frequency (48 KHz) to drive a timer/counter which then uses shared memory IPC (interprocess communication) to display the time on the VGA. The both the audio and video code were attached to the same shared memory segment using shmget and shmat. As before, the audio code required the math library for sine wave synthesis, which requires compile with the -lm option. (Quartus archiveaddress header). 

-- A minor modification of both the audio and video code plays a one-octave scale on the audio side and displays the time and frequency on the video side.

-- Cleaning up both the audio and video code puts pixel limit error checking in the video draw routines and better naming in audio program.

-- Adding a disk draw function (video) to the video code makes particle systems nicer.

See web page for more details and examples

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